This invention relates generally to electronic circuits, and more particularly the invention relates to self-timing clocked circuits in which clock signal periods are variable.
Combinatorial logic circuits operate in response to clock signals in operating on input data or numbers. The length of the clock period of a typical integrated circuit is determined by a time which is needed to obtain complete stability of all logic states in the longest or critical path of the circuit. In an adder, for example, the time to add two random numbers can vary greatly depending on the number of carry signals. However, if such worse case conditions for processing numbers occur infrequently in the circuit, then during a large percentage of clock periods the circuit is clocked too slowly and the circuit experiences considerable idle time.